rai o RA8875 character/graphic tft lcd controller specification version 1.0 march 27, 2013 ra i o technology inc. ? copyright raio technology inc. 2010, 2011, 2012, 2013 rai o technology inc. www.raio.com.tw 1/9
version 1.0 character / graphic tft lcd controller RA8875 1 description RA8875 is a text/graphic mixed display with 2 layers tft lcd controller. it is designed to meet the requirement of middle size tft module up to 800x480 pixels with characters or 2d graphic application. embedded 768kb display ram provides user a flexible solution for displaying buffer of almost application. besides, optional external serial flash is capable to provide the up to 32x32pixels font bitmap for big5/gb coding. for graphic usage, RA8875 supports a 2d block tr ansfer engine(bte) that is compatible with 2d bitblt function for processing the mass data transf er. the advanced geometric speed-up engine provides user an easy way to draw the programmable geometric s hape by hardware, like line, square, circle and ellipse. besides, for different end-user applications, many powe rful functions are integrated with RA8875, such as scroll function, floating window display, graphic pattern and font enlargement function. these functions will save user a large of software effort during development period. RA8875 is a powerful and cheap choice for color displa y application. to reduce the system cost, RA8875 provides low cost and easy-to-use 8080/6800 parallel mcu interface. because of the powerful hardware speed-up function embedded in it, less data transfer is needed so more efficiency is improved, RA8875 also provides serial spi/i2c i/f with ultra- low pin-count. useful device controller, such as flexible 4-wire touch panel controller, pwm for adjusting panel back-light are also in cluded to reduce the system cost for customer. with the RA8875 design-in, user can achi eve an easy-to-use, low-cost and hi gh performance system comparing with the other solution. 2 feature ? support text/graphic mixed display mode. ? embedded 768kb ddram. ? color depth tft: 256/4k/65k colors. ? supporting tft 8/12/16 bpp generic rgb interface. ? supporting tft panel size: ? 800x480 pixels 2 layers @ 256 colors. ? 800x480 pixels 1 layer @ 64k colors. ? 480x272 pixels 2 layers @ 64k colors. ? supporting mpu interface : ? 8080/6800 with 8/16 data bus width ? i2c or 3/4-wires spi i/f. ? powerful block scrolling function for vertical or horizontal direction. ? embedded 10kb character rom with font size 8x16 dots and supporting character set of iso/iec 8859-1/2/3/4. ? external serial flash/rom spi i/f supporting. ? supporting genitop unicode/big5/gb serial font rom with 16x16/24x24/32x32 dots font size. ? font enlargement functi on x1, x2, x3, x4 for horizontal/vertical direction. ? font vertical rotation mode function. ? block transfer engine (bte) supports with 2d function, compatible with 2d bitblt function. ? embedded geometric speed-up engine. ? programmable text cursor for writing with character. ? 32*32 pixel graphic cursor function. ? user-defined characters. ? 256 characters with 8*16 dots. ? supporting 32 user-defined patterns of 8*8 pixels, or 16 user-defined pattern for 16*16 pixels. ? two programmable pwm for back-light adjusting or other's application. ? embedded 4-wire touch panel controller. ? sleep mode with low power consumption. ? embedded smart 4*5 key-scan controller. ? 4 sets of programmable gpo and a fixed gpox. ? 5 sets of programmable gpi and a fixed gpix ? clock source: embedded crystal oscillator circuit with programmable pll. ? operation voltage: 3.0v~3.6v. ? package: lqfp-100pin. rai o technology inc. www.raio.com.tw 2/9
version 1.0 character / graphic tft lcd controller RA8875 3 block diagram mpu i/f block register block 2d-bte engine ddram scroll engine geometric speed-up engine rst# test[2:0] db[15:0] rd#/en# wr#/rw# cs# rs c86 wait# int# test circuit sfcl sfdi sfdo sfcs0# sfcs1# serial flash/rom if xp xn yp yn adc_vref 4 wires touch panel controller adc reset control xi xo osc font engine generic tft driver i/f pdat[15:0] hsync vsync pclk de kout [3:0]/ gpo [3:0] kin [4:0]/ gpi [4:0] gpox gpix keyscan controller pll i2c/spi scl sdi/sda sdo scs# sifs0 sifs1 iica[1:0] cgrom pattern/ cursor pwm pwm1 pwm2 mpu i/f block register block 2d-bte engine ddram scroll engine geometric speed-up engine rst# test[2:0] db[15:0] rd#/en# wr#/rw# cs# rs c86 wait# int# test circuit sfcl sfdi sfdo sfcs0# sfcs1# serial flash/rom if xp xn yp yn adc_vref 4 wires touch panel controller adc reset control xi xo osc font engine generic tft driver i/f pdat[15:0] hsync vsync pclk de kout [3:0]/ gpo [3:0] kin [4:0]/ gpi [4:0] gpox gpix keyscan controller pll i2c/spi scl sdi/sda sdo scs# sifs0 sifs1 iica[1:0] cgrom pattern/ cursor pwm pwm1 pwm2 4 system block diagram RA8875 tft lcd module pwm 8/16 bits mpu 4 wires touch panel spi /i 2 c serial flash keypad /gpio RA8875 tft lcd module pwm 8/16 bits mpu 4 wires touch panel spi /i 2 c serial flash keypad /gpio rai o technology inc. www.raio.com.tw 3/9
version 1.0 character / graphic tft lcd controller RA8875 5 pin definition 5-1 mpu interface pin name i/o pin description db[15:0] io data bus these are data bus for data transfer between mpu and RA8875. when setting register number and register data, db[7:0] is used. when writing data to display ram, db[15:0] is used according to data bus mode setting. db[15:8] will be input and should be pull-low or pull-high when 8-bits data bus mode is used. rd# (en) i enable/read enable when mpu interface (i/f) is 8080 series, this pin is used as rd# signal (data read) , active low. when mpu i/f is 6800 series, this pin is used as en signal (enable), active high. wr# (rw#) i write/read-write when mpu i/f is 8080 series, this pin is used as wr# signal (data write) , active low. when mpu i/f is 6800 series, this pin is used as rw# signal (data read/write control) . active high for read and active low for write. cs# i chip select input low active chip select pin. rs i command / data select input the pin is used to select command/ data cycle. rs = 0, data read/write cycle is selected. rs = 1, status read/command write cycle is selected. in 8080 interface, usually it connects to ?a0? address pin. rs wr# access cycle 0 0 data write 0 1 data read 1 0 cmd write 1 1 status read c86 i mpu interface select 0: 8080 interface is selected 1: 6800 interface is selected ps i parallel /serial i/f select input 0: parallel 8080/6800 i/f select 1: serial 3/4-wire spi or iic i/f select. ps input is used to select the active mcu interface, it must be set correctly before the command /data cy cle asserting. we also recommend that db[15:0] , rd#(en) , wr#(rw#) , cs# and rs pin tie to low or high when using serial i/f. int# o interrupt signal output the interrupt output for mpu to indicate the status of RA8875. wait# o wait signal output this is a wait# output to indicate the RA8875 is in busy state. the RA8875 can?t access mpu cycle when wait # pin is active. it is active low and could be used for mpu to poll busy status by connecting it to i/o port. rai o technology inc. www.raio.com.tw 4/9
version 1.0 character / graphic tft lcd controller RA8875 5-2 serial mcu interface pin name i/o pin description scl o spi clock 3-wires, 4-wires serial or iic i/f clock. sdi (sda) i/o 4-wires spi data input/3-wire spi data 4-wires spi i/f: data input for serial i/f. 3-wires spi or iic i/f: bi-direction data for serial i/f. sdo o spi data output 4-wires spi i/f: data output for serial i/f. 3-wires spi or iic i/f: nc, if no use, please keep floating. scs# o spi chip select chip select pin for 3-wires or 4-wires serial i/f. iic i/f : nc, please connect it to vddp. iica[1:0] i iic i/f: iic address select. other i/f: nc, please connect it to vddp. sifs[1:0] i serial interface selection 00 : nc. 01 : 3-wire spi 10 : 4-wire spi 11 : iic 5-3 lcd panel interface pin name i/o pin description pdat[15:0] o lcd panel data bus tft lcd data bus output for gate driver. RA8875 support 256/4k/64k color depth by register (reg[10h]), user can connect corresponding rgb bus for different setting. for unused pin please keep it as floating. color depth red green blue 256 pdat[15:14] pdat[10:8] pdat[4:3] 4k pdat[15:12] pdat[10:7] pdat[4:1] 64k pdat[15:11] pdat[10:5] pdat[4:0] hsync o hsync pulse generic tft interface signal. vsync o vsync pulse generic tft interface signal. pclk o pixel clock generic tft interface signal. de o data enable generic tft interface signal. rai o technology inc. www.raio.com.tw 5/9
version 1.0 character / graphic tft lcd controller RA8875 5-4 serial flash / rom interface pin name i/o pin description sfcl o external serial flash/rom clock serial flash/rom spi i/f clock. sfdi/sio0 i/o external flash/rom spi data input single mode: data input for serial flash/rom spi i/f. dual mode: the signal is used as bi-direction data #0(sio0). sfdo/sio1 i/o external flash/rom spi data output single mode: data output for serial flash/rom spi i/f. dual mode: the signal is used as bi-direction data #1(sio1). sfcs0# o external flash/rom spi chip select 0 chip select pin for serial flash/rom spi i/f #0. sfcs1# o external flash/rom spi chip select 1 chip select pin for serial flash/rom spi i/f #1. 5-5 touch interface pin name i/o pin description yn a yn signal for touch panel 4-wire tp yn control signal. yp a yp signal for touch panel 4-wire tp yp control signal. xn a xn signal for touch panel 4-wire tp xn control signal. xp a xp signal for touch panel 4-wire tp xp control signal. adc_vref a tp adc reference voltage this pin is the reference voltage for adc as 0.5 vdd. the reference voltage could be generated by RA8875(default) or from external circuit. 5-6 keyscan interface pin name i/o pin description kout[3:0]/ (gpo[3:0]) o keypad strobe line or gpos(general purpose output) keypad matrix strobe lines outputs with open-drain. (default). they could be programmed as gpos by register setting , if don?t use, please keep floating. kin[4:0]/ (gpi[4:0]) i keypad data line or gpis (general purpose input) keypad data inputs(default), please add pull-up resister. they could be programmed as gpis by register setting, if don?t use, please connect it to gnd. gpox 0 extra gpo(general purpose output) additional gpo signal. if don?t use, please keep floating. gpix i extra gpi(general purpose input) additional gpi signal, if don?t use, please connect it to gnd. rai o technology inc. www.raio.com.tw 6/9
version 1.0 character / graphic tft lcd controller RA8875 5-7 keyscan interface pin name i/o pin description pwm1 o pwm signal output 1 pwm2 o pwm signal output 2 5-8 clock and power interface pin name i/o pin description xi i crystal input pin input pin for internal crystal circuit. it should be connected to external crystal circuit. that will generat e the system cl ock for RA8875. xo o crystal output pin output pin for internal crystal circ uit. it should be connected to external crystal circuit. that will generat e the system cl ock for RA8875. rst# i reset signal input this active-low input performs a hardware reset on the RA8875. it is a schmitt-trigger input with pull-up resistor for enhanced noise immunity; however, care should be taken to ensure that it is not triggered if the supply voltage is lowered. test[2:0] i test mode input for chip test function, should be connected to gnd for normal operation. vddp p io vdd 3.3v io power input. core_vdd p core vdd 1.8 v core power input. ldo_vdd p ldo vdd output 1.8v power generated by internal ldo. it must connect bypass capacities to prevent power noise. osc_vddp p osc io vdd the separated osc 3.3v io power. osc_vdd p osc vdd osc 1.8 v power output. it is used by osc core. it is suggested to connect the bypass capacitor nearby the pad. osc_gndp p osc io gnd the separated osc io ground signal. osc_gnd p osc gnd osc ground signal and are inter nally connected to osc_gndp. adc_vdd p adc vdd adc 3.3v power signal. adc_gnd p adc gnd adc ground signal gnd p gnd io cell/core ground signal rai o technology inc. www.raio.com.tw 7/9
version 1.0 character / graphic tft lcd controller ra o technology inc. www.raio.com.tw 8/9 RA8875 6 package raio tm RA8875l3n osc_gndp osc_vddp xi xo osc_vdd osc_gnd wait# int# rst# test0 test1 test2 vddp pwm1 pwm2 gnd core_vdd sfcl sfdi sfdo sfcs0# sfcs1# iica0 iica1 ps 51 0 15 20 25 de pclk vsync hsync gpox gpix scl sdi sdo scs# vddp gnd core_vdd kin0 / gpi0 kin1 / gpi1 kin2 / gpi2 kin3 / gpi3 kin4 / gpi4 kout0 / gpo0 kout1 / gpo1 kout2 / gpo2 kout3 / gpo3 sifs0 sifs1 gnd 30 35 40 45 50 xp yn yp xn adc_vref adc_gnd pdat15 pdat14 pdat13 pdat12 pdat11 pdat10 pdat9 vddp ldo_gnd ldo_out pdat8 pdat7 pdat6 pdat5 pdat4 pdat3 pdat2 pdat1 pdat0 55 60 65 70 75 adc_vdd rd# / en wr# / rw# cs# rs c86 db0 db1 db2 gnd core_vdd vddp db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 80 85 90 95 1020-n date code (year 2010, 20th week) 100 1 26 51 76 i
version 1.0 character / graphic tft lcd controller RA8875 item resolution color parallel mcu i/f serial mcu i/f int. ddram ext. ddram t/p 2d + bte ascii ext font rom key-scan gpio pakage ra8870 640x480 65k 8/16 bit -- 270kb 1mb parallel 4/5-wries y y 1mb parallel -- 6 lqfp-128, die RA8875 800x480 65k 8/16 bit 3/4/iic 768kb -- 4- wires y y 1mb serial 4x5 7 lqfp-100, die RA8875 vs. ra8870 1 remove 5-wires t/p. 2 remove dac and analog panel i/f. 3 embedd ddram up to 768kbytes. 4 two pages for 320x240 65k-colors. 5 no external ddram i/f. 6 change parallel font rom to genitop serial font rom. 7 geometric speed-up engine support ?ellipse? function. 8 add 3/4-wires spi, iic . 9 add 4x5 smart key-scan controller for multi-key press. 10 packahe tqfp-128pins change to tqfp-100pins. rai o technology inc. www.raio.com.tw 9/9
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